
Himanshu S. Amin
Managing Partner
Cleveland
BS Electrical Engineering · USPTO reg.

Semiconductors & Electronics
Semiconductor patents fail in predictable ways: a claim tied to a process node that moves, a structural limitation that a competitor's integration scheme sidesteps, a specification that never enabled the corner case. Avoiding those requires drafting from an understanding of how the device is actually built.
We prosecute and litigate across the semiconductor stack — device physics and structures, analog and mixed-signal circuits, memory, power electronics, packaging and interconnect, fabrication process and equipment, and the metrology around them. The same coverage extends to consumer electronics, displays, imaging and optoelectronics, and RF and antenna systems.
That coverage shows in the portfolios we manage: system-on-chip architectures, memory cell structures, photolithography and deposition processes, and the analog circuitry that surrounds them.
A structural limitation calibrated to one node becomes a design-around instruction two nodes later. Semiconductor claims hold their value when they recite the functional relationship that makes the structure work — the doping relationship, the interface behavior, the thermal path — rather than the dimension that happened to be current when the application was filed.
Getting there requires reading the process flow, not the invention disclosure summary. It is why the drafting is done by people with the underlying training.
A claim covering an internal process step is a claim nobody can prove is infringed without a fab tour. Claims that read on the finished device — something visible in cross-section, in a die photograph, or in electrical characterization — are the ones that can be asserted. A portfolio needs both, and needs to know which is which before it needs to enforce anything.
Evidence
Team

Managing Partner
Cleveland
BS Electrical Engineering · USPTO reg.

Managing Partner
Cleveland
MS Organic Chemistry · USPTO reg.

Managing Partner
Seattle
BS Electrical Engineering · USPTO reg.

Partner
Fairfax
BS Computer Science · USPTO reg.

Partner
Las Vegas
BS Electrical Engineering · USPTO reg.

Partner
San Jose
BS Electrical Engineering · USPTO reg.

Partner
Ft. Lauderdale
BS Molecular and Micro Biology · USPTO reg.
Partner
Seattle
BS Physics · USPTO reg.

Partner
Cleveland
BS Electrical Engineering · USPTO reg.

Partner
San Jose
BS Systems Engineering · USPTO reg.

Partner
Atlanta
BS Electrical Engineering · USPTO reg.

Associate
Atlanta

Associate
Cleveland
BS Biomedical Engineering · USPTO reg.

Associate
Cleveland
MS Computer Science

Associate
Seattle
BS Electrical Engineering · USPTO reg.

Associate
Seattle
BS Chemical Engineering

Associate
Cleveland
BS Industrial & Systems Engineering · USPTO reg.

Associate
Cleveland
BS Computer Engineering · USPTO reg.

Patent Agent
Ft. Lauderdale
BS Computer Software/Hardware Engineering · USPTO reg.

Patent Agent
New York
BS Mathematics and Computer Science

Patent Agent
Columbus
BS Electrical Engineering · USPTO reg.